MainWindow 0 0 839 808 MainWindow 0 0 0 0 0 UART Open Refresh false Close false Save Setting false 0 Timeout(ms): Qt::AlignCenter false 8 5 6 7 false 1 1.5 2 Data Bits： Qt::AlignCenter Stop Bits： Qt::AlignCenter false None Even Odd Mark Space false 360000 9000000 1200 2400 4800 9600 19200 38400 57600 11520 Baud Rate： Qt::AlignLeading|Qt::AlignLeft|Qt::AlignVCenter Parity Bits: Qt::AlignLeading|Qt::AlignLeft|Qt::AlignVCenter 0 0 UART Device List： Qt::AlignLeading|Qt::AlignLeft|Qt::AlignVCenter SPI SPI Device List： Qt::AlignCenter false LSB MSB false 8 16 SPI Mode: Qt::AlignCenter 0 0 Save Setting false Close false 60MHz 30MHz 15MHz 7.5MHz 3.75MHz 1.875MHz 937.5MHz 468.75MHz Clock: Qt::AlignCenter LSB/MSB Qt::AlignCenter false Mode0 Mode1 Mode2 Mode3 DataBits: Qt::AlignCenter false CS1_POLA_LOW CS1_POLA_HIGH false CS2_POLA_LOW CS2_POLA_HIGH Open Refresh 0 0 Mode Swtich: Voltage Check Import Voltage From File Read Voltage From Chip 16 16 Start Calibrate Qt::Horizontal QSizePolicy::MinimumExpanding 40 20 0 0 Log true 0 0 Clear UART SPI 0 0 Chip Test FBK_EN Reg Value Reg 3: Reg 6: Reg 2: Reg 5: Reg 4: Reg 1: TRIG_TADC Read Reg 1000 0000 0001 0010 0011 0100 0101 0110 0111 1001 1010 1011 1100 1101 1110 1111 DAC Channel #: TEST_EN true 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 01 00 10 11 DAC # ICON18: EN_TADC true TEMPTEST_EN Write Reg N_CLKDIV18: 1 256 0 0 839 21